Technology scaling has led to the development of fin-based field-effect transistor (FET) structures as an alternative to the bulk-Silicon (or bulk-Si) metal-oxide-semiconductor FET structure for performance enhancements. The fin-based FET utilizes a silicon fin to wrap the conducting channel, which forms the body of the transistor. In effect, the gate electrode of the transistor straddles or surrounds the fin. During operation, current flows between the source and drain electrodes of the transistor along the gated sidewall surfaces of the fin.
A consequence of FET device scaling is a requirement to reduce operating voltages. The reduced operating voltages are required because FET device scaling needs a relatively thin gate dielectric layer to produce the desired electrical characteristics in the scaled-down transistor. Although the thinner gate dielectric provides a relatively large cutoff frequency band at high frequencies, the reliability of thinner gate dielectrics becomes increasingly limited by time-dependent dielectric breakdown (TDDB), hot carrier injection (HCI), and negative bias temperature instability (NBTI) factors. Without a reduction in operating voltage, the electrical field impressed across the thinner gate dielectric during circuit operation can be relatively high enough for dielectric breakdown to become a problem.
Integrated circuit designs may require both low operating voltage FETs for their ability to operate at high frequencies, and high operating voltage FETs for their ability to interface with high voltage signals of auxiliary devices. However, integrated circuit design techniques often increase the fabrication cost and/or complexity by requiring additional process steps along with additional substrate masking.